In military electronic equipment such as missiles, for example, there is a requirement for a precision clock system which has the capability of designating absolute time despite short periods of functional disability of the electronic counting circuits in the clock system as the missile passes through a nuclear explosion region. Such periods usually are of the order of about 2 milliseconds, and are sufficient seriously to impair the navigational guidance control of the missile.
The prior art absolute clock systems ususally include a quartz crystal oscillator and associated electronic circuitry including a counter. During the period of time when the radioactive level is too high for the proper functioning of the electronic circuitry in the system, the prior art system has no means for determining the absolute elasped time during which the electronic circuitry was inactive.
However, due to its high mechanical inertia, the quartz crystal continues to vibrate during the interval without significant loss of phase reference data. Accordingly, the quartz crystal oscillations after the interruption continue to be in phase with its oscillations before the interruption. However, as mentioned above, in the prior art clock systems, there is no means for determining how many cycles of the crystal occurred during the interruption.
The principal objective of the present invention is to provide a multi-stage quartz crystal absolute clock system in which the mechanical inertia of the quartz crystal in each of its stages is used to determine absolute time, which determination is not impaired, even in the presence of an interruption in the functioning of the associated electronic circuitry, and even when such interruption is relatively long as compared with the period of oscillation of the various crystals.
In order to achieve the objectives of the present invention it is necessary for several requirements to be met. Specifically, the absolute clock system must contain a quartz crystal precision master oscillator whose operating frequency is sufficiently high so as to provide adequate time resolution; the clock must operate at a basic frequency which is sufficiently low so as to prevent ambiguity during an operation; and the frequency determining elements of the clock must be of a sufficiently high mechanical "Q" so that they will accurately track time during the period when the electronic circuitry is inoperative and provide a signal of the correct absolute phase on recovery of the electronic capability. The usual prior art electronic counter circuits cannot be employed in the absolute clock system of the invention since they acquire spurious numbers on reactivation after an interruption, so as to be no longer operational as a means for determining absolute time.
In the embodiment of the system of the present invention to be described, a master oscillator clock is provided which generates an output of 10 MHz, so that the frequency of the least significant bit (LSB) of the digital clock output signal is 10 MHz. The system of the invention also employs a number of cascaded counter stages which are interconnected and operate, for example, so that the most significant bit (MSB) of the digital output signal has a frequency of 153 Hz. In the system, each counter stage serves to divide down the master oscillater clock frequency from the frequency of the LSB to the frequency of the MSB.
The requirements for an absolute clock system which is capable of operation through the time interval of a nuclear event without loss of integrity are met in the system of the present invention by providing a master crystal oscillator at the highest required clock frequencies (10 MHz) with a sufficiently high "Q" so that phase accuracy will not be lost during an interruption of operation of the electronic circuitry; and a plurality of auxiliary crystal oscillators in the respective count-down stages which, in normal operation, are phase locked to suitable sub-multiples of the master oscillator. The count-down stages provide the various bits of the digital clock output of the absolute clock system of the invention. Each auxiliary crystal oscillator is required to have a sufficiently high "Q" to maintain its phase relationship to the next higher frequency auxiliary crystal oscillator during the period of interruption. Since the lower frequencies which are required to produce the higher significant bits in the digital clock output are unattainable directly with oscillators, these frequencies are obtained in the system to be described by beating two oscillator frequencies together in order to obtain a low value difference frequency.